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PDI1284P11
3.3 V parallel interface transceiver/buffer
Rev. 03 -- 25 August 2008 Product data sheet
1. General description
The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bidirectional, parallel interface for personal computers. The PDI1284P11 includes all 19 signal lines defined by the IEEE 1284 interface specification for Byte, Nibble, EPP, and ECP modes. The PDI1284P11 is designed for hosts or peripherals operating at 3.3 V to interface 3.3 V or 5.0 V devices. The eight transceiver pairs (A/B 1 to 8) allow data transmission from the A-bus to the B-bus, or from the B-bus to the A-bus, depending on the state of the direction pin DIR. The B-bus and the Y9 to Y13 lines have either totem pole or resistor pull-up outputs, depending on the state of the high drive enable pin HD. The A-bus has only totem pole style outputs. All inputs are TTL compatible with at least 400 mV of input hysteresis at VCC = 3.3 V.
2. Features
I I I I I I Asynchronous operation 8-bit transceivers Six additional buffer/driver lines peripheral to cable Five additional control lines from cable 5 V tolerant ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V Latch-up current protection exceeds 500 mA per JEDEC Std 19 Input hysteresis Low-noise operation IEEE 1284 compliant level 1 and 2 Overvoltage protection on B/Y side for off-state A side 3-state option B side active or resistive pull-up option Cable side supply voltage for 5 V or 3 V operation
I I I I I I I I
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
3. Ordering information
Table 1. Ordering information Package Temperature range Name PDI1284P11DL PDI1284P11DGG 0 C to 70 C 0 C to 70 C SSOP48 TSSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm plastic thin shrink small outline package; 48 leads; body width 6.1 mm Version SOT370-1 SOT362-1 Type number
PDI1284P11_3
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Product data sheet
Rev. 03 -- 25 August 2008
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PDI1284P11
3.3 V parallel interface transceiver/buffer
4. Functional diagram
HD
HD
CNTL HD HD HD HD HD HD
DIR OEA Y9 Y10 Y11 Y12 Y13
A9 A10 A11 A12 A13
A1 CNTL HD A2 CNTL HD A3 CNTL HD A4 CNTL HD A5 CNTL HD A6 CNTL HD A7 CNTL HD A8 CNTL PLHI A14 A15 A16 A17 HLHO
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B1
B2
B3
B4
B5
B6
B7
B8 HD
PLHO C14 C15 C16 C17 HLHI
Fig 1.
Logic symbol
PDI1284P11_3
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Product data sheet
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3 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
5. Pinning information
5.1 Pinning
HD A9 A10 A11 A12 A13 VCC A1 A2
1 2 3 4 5 6 7 8 9
48 DIR 47 Y9 46 Y10 45 Y11 44 Y12 43 Y13 42 VCC(B) 41 B1 40 B2 39 GND 38 B3 37 B4 36 B5 35 B6 34 OEA 33 B7 32 B8 31 VCC(B) 30 PLHO 29 C14 28 C15 27 C16 26 C17 25 HLHI
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GND 10 A3 11 A4 12 A5 13 A6 14 GND 15 A7 16 A8 17 VCC 18 PLHI 19 A14 20 A15 21 A16 22 A17 23 HLHO 24
PDI1284P11
Fig 2.
Pin configuration
5.2 Pin description
Table 2. Symbol HD A1 to A8 B1 to B8 A9 to A13 Y9 to Y13 C14 to C17 A14 to A17 VCC GND PLHI
PDI1284P11_3
Pin description Pin 1 8, 9, 11, 12, 13, 14, 16, 17 41, 40, 38, 37, 36, 35, 33, 32 2, 3, 4, 5, 6 29, 28, 27, 26 20, 21, 22, 23 7, 18 10, 15, 39 19 Description high drive enable/disable input data input/output IEEE 1284 standard output/input[1] data input control input (cable)[1] control output (peripheral) supply voltage ground (0 V) peripheral logic high input (peripheral)
(c) NXP B.V. 2008. All rights reserved.
47, 46, 45, 44, 43 IEEE 1284 standard output[1]
Product data sheet
Rev. 03 -- 25 August 2008
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NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
Table 2. Symbol HLHO HLHI PLHO VCC(B) OEA DIR
[1]
Pin description ...continued Pin 24 25 30 31, 42 34 48 Description host logic high output (cable) host logic high input (cable) peripheral logic high output (cable) supply voltage B (cable side 3 V/5 V) A side output enable input (active LOW) direction selection input
Pin with pull-up resistor to load cable.
6. Functional description
6.1 Function selection
Table 3. DIR X X X X X X H H L L L
[1]
Function table[1] OEA X X X X X X X X L H H HD X X L H L H L H X X X Input C14 to C17 HLHI A9 to A13 A9 to A13 PLHI PLHI A1 to A8 A1 to A8 B1 to B8 B1 to B8 Output A14 to A17 HLHO Y9 to Y13 Y9 to Y13 PLHO PLHO B1 to B8 B1 to B8 A1 to A8 A1 to A8 Output type TP TP RP TP OC TP RP TP TP Z[2] RP[2]
An = side driving internal IC; Bn = side driving external cable (bidirectional); Cn = side receiving control signals from external cable; H = HIGH voltage level; L = LOW voltage level; OC = Open Collector; X = don't care (control signals in); Yn = side driving external cable (unidirectional); Z = high impedance (high-Z) or 3-state; TP = totem pole output; RP = resistive pull-up: 1.4 k (nominal) on B/Y/C cable side and VCC. However, while a B/Y side output is LOW as driven by a LOW signal on the A side, that particular B/Y side resistor is switched off to stop current drain from VCC through it. When DIR = L and OEA = H, the output signal is isolated from the input signal. Signals B1 to B8 maintain a resistive pull-up of 1.4 k on the input for this mode.
[2]
PDI1284P11_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
5 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VCC VCC(B) IIK IOK VI VO Vtrt ICC IGND IO Tstg Ptot
[1] [2] [3] [4]
Parameter supply voltage supply voltage B input clamping current output clamping current input voltage output voltage transient voltage supply current ground current output current storage temperature total power dissipation
Conditions pins VCC pins VCC(B); cable side 3 V/5 V VI < 0 V VO < 0 V
[2]
Min -0.5 -0.5 -0.5 -0.5 -0.5
[3] [2]
Max +4.6 +6.5 20 50 +5.5 +5.5 VCC + 0.5 +7 200 50 +150 500
Unit V V mA mA V V V V mA mA mA C mW
B/Y side A side B/Y side; 40 ns transient
-2 -200
output HIGH or LOW Tamb = 0 C to +70 C
[4]
-60 -
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Vtrt guarantees only that the PDI1284P11 will not be damaged by reflections in application so long as the voltage levels remain in the specified range. Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5. Symbol VCC VCC(B) VIH VIL VO IOH IOL Tamb Operating conditions Parameter supply voltage supply voltage B HIGH-level input voltage LOW-level input voltage output voltage HIGH-level output current LOW-level output current ambient temperature pins Bn, Yn pins An pins Bn, Yn pins Bn, Yn free-air Conditions pins VCC pins VCC(B); cable side 3 V/5 V Min 3.0 3.0 2.0 -0.5 0 0 Max 3.6 5.5 0.8 +5.5 VCC -14 14 70 Unit V V V V V V mA mA C
PDI1284P11_3
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Product data sheet
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NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
9. Static characteristics
Table 6. Static characteristics Tamb = 0 C to 70 C; ground = 0 V; unless specified otherwise. Symbol Parameter VIL VIH LOW-level input voltage Conditions An, Bn, Cn and PLHI inputs; VCC = 3.0 V to 3.6 V HLHI input; VCC = 3.0 V Min 2.0 2.3 2.6
[1] [1]
Typ -
Max 0.8 1.55 -
Unit V V V V V V V V V V V V V V V A A
HIGH-level input An, Bn, PLHI inputs; VCC = 3.0 V to 3.6 V voltage Cn inputs; VCC = 3.0 V to 3.6 V HLHI input; VCC = 3.6 V hysteresis voltage LOW-level output voltage An, Bn inputs; VCC = 3.3 V; VIL = 0.8 V; VIH = 2.0 V Cn inputs; VCC = 3.3 V pins An, HLHO; IOL = 50 A; VCC = 3.0 V pins An, HLHO; IOL = 4 mA; VCC = 3.0 V pins Bn, Yn; IOL = 14 mA; VCC = 3.0 V pin PLHO; IOL = 500 A; VCC = 3.0 V
VH VOL
0.4 0.8 2.8 2.4 2.23 3.1
0.47 0.47 5 0.1 0.2 0.4 0.77 0.8 100
VOH
HIGH-level output voltage
pins An, HLHO; IOH = -500 A; VCC = 3.0 V pins An, HLHO; IOH = -4 mA; VCC = 3.0 V pins Bn, Yn; IOH = -14 mA; VCC = 3.0 V pin PLHO; IOH = 500 A; VCC = 3.15 V
ICC
supply current
VI = 0 V or VCC; IO = 0 A pins VCC and VCC(B); VCC = 3.6 V; VCC(B) = 3.6 V to 5.5 V; VI = 0 V or VCC; pins Bn = VCC(B); pins Cn = VCC(B) or floating pins VCC(B); VCC = 3.6 V; VI = 0 V or VCC; pins Cn = 0 V pin DIR = 3.6 V; VCC(B) = 3.6 V pin DIR = 3.6 V; VCC(B) = 5.5 V pin DIR = 0 V; VCC(B) = 3.6 V; pins Bn = 0 V pin DIR = 0 V; VCC(B) = 5.5 V; pins Bn = 0 V
[1]
-
[2]
[3]
10 16 30 47 -
15 20 40 60 100 100 1 20
mA mA mA mA A A A A
IOFF
power-off leakage current
pins Bn, Cn, Yn; VO = 5.5 V; VCC = 0 V VCC(B) = 0 V VCC(B) = 4.5 V VI = 0 V to VCC 3-state; VO = VCC or 0 V VCC = 3.3 V; see Figure 9 VO = 1.65 V 0.1 V; B/Y side B/Y side; VCC = 3.3 V; output in high-Z with resistive pull-up
[1] [1]
II IOZ Ro RPU
input leakage current OFF-state output current output resistance pull-up resistance
-
[3]
35 1.15
45 1.4
55 1.65
k
[1] [2] [3]
Typical values at Tamb = 25 C. Includes extra ICC(B) current from pull-up resistors, i.e. ICC(B) = (total number of LOW inputs on B and C sides) x (VCC(B) / RPU). The pull-up resistor on the B side outputs makes it impossible to test IOZ on the B side. This applies to the input current on the C side inputs as well.
PDI1284P11_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
7 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
10. Dynamic characteristics
Table 7. Dynamic characteristics VCC = 3.0 V to 3.6 V; ground = 0 V; CL = 50 pF; RL = 500 ; Tamb = 0 C to 70 C; unless specified otherwise. Symbol tPLH tPHL tpd Parameter LOW to HIGH propagation delay HIGH to LOW propagation delay propagation delay Conditions An to Bn or Yn; see Figure 3 and 8 An to Bn or Yn; see Figure 3 and 8 see Figure 4 and 8 Bn to An Cn to An PLHI to PLHO HLHI to HLHO SR tdis slew rate disable time Bn/Yn; RL = 62 ; see Figure 5 and 8 HD to Yn or Bn; see Figure 6 and 8 HD to PLHO; see Figure 6 and 7 RL = 250 ; see Figure 6 and 7 DIR to Bn; TP load on B/Y side DIR to An OEA to An ten enable time HD to Yn or Bn; see Figure 6 and 7 HD to PLHO; see Figure 6 and 7 RL = 250 ; see Figure 6 and 7 DIR to Bn; TP load on B/Y side DIR to An OEA to An tPD propagation delay difference tPZH - tPHZ; HD to output
[4] [4] [4] [3] [3] [3] [1]
Min 0 0
Typ[2] 12.5 13.9
Max 20 23
Unit ns ns
0 0.05 -
0.2 -
12 15 20 15 0.4 20 20 50 15 6 20 20 30 50 12 10
ns ns ns ns V/ns ns ns ns ns ns ns ns ns ns ns ns
[1] [2] [3] [4]
tpd is the same as tPLH and tPHL. Value at Tamb = 25 C and VCC = 3.3 V. tdis is the same as tPHZ and tPLZ. ten is the same as tPZH and tPZL.
PDI1284P11_3
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Product data sheet
Rev. 03 -- 25 August 2008
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PDI1284P11
3.3 V parallel interface transceiver/buffer
11. Waveforms
2.4 V input 1.4 V 1.4 V 0.4 V tPLH output 1.4 V tPHL VO VO - 1.4 V
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Fig 3.
Input An to output Bn or Yn propagation delays
VI input GND tPHL VOH output VOL
001aai292
VM
tPLH
VM
VM = 1.5 V. VCC never goes below 3.0 V. VOL and VOH are the typical voltage output levels that occur with the output load.
Fig 4.
Input Bn, Cn to output An propagation delays
2.4 V input 0.4 V 0.9 V output 0.4 V t1 t2 t1 t2 1.9 V
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2.4 V
Measurement data is given in Table 8. SR is measured for both a LOW-to-HIGH and a HIGH-to-LOW transition.
Fig 5. Table 8. tr 3 ns
Slew rate on B/Y side Slew rate measurements tf 3 ns tW 150 ns < tW < 10 s RL 62 VO transition (see Figure 8) Rising from VO = 0.4 V to VO = 0.9 V Falling from VO = 2.4 V to VO = 1.9 V
PDI1284P11_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
9 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
DIR to A
VM
DIR to B
VM
VI HD to B GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
001aai294
VM
tPZL
VM VX tPZH VY VM
Test circuit is shown in Figure 7. Measurement points are given in Table 9. VOL and VOH are the typical voltage output levels that occur with the output load.
Fig 6.
Enable and disable times
VEXT VCC VI VO DUT
RT CL RL RL
G
mna616
Test conditions are given in Table 9.
Fig 7. Table 9.
Test circuit for measuring enable and disable times Test data for test circuit measuring enable disable times Bn to An VCC < 2.7 V 2.7 V to 3.6 V < 2.7 V 2.7 V to 3.6 V Input VI VM 1.5 V 1.5 V 1.5 V 1.5 V VCC 2.7 V VCC 2.7 V Output VM 1.5 V 1.5 V 1.5 V 1.5 V VX VOL 0.3 V VOL 0.3 V VY VOH - 0.3 V VOH - 0.3 V VOH - 0.3 V VOH - 0.3 V VEXT tPZH, tPHZ GND GND open open tPZL, tPLZ 2VCC 2VCC -
Parameter DIR to Bn, An; OEA to An HD to Yn or Bn; HD to PHLO
PDI1284P11_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
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NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
VI negative pulse 0V
tW 90 % VM 10 % tf tr VM 10 % tr tf 90 % VM 10 % tW
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90 %
VI positive pulse 0V
90 % VM 10 %
a. Input pulse definition
VCC
CL VI VO
G
VEXT GND
DUT
RT RL
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b. Test circuit
CL = load capacitance includes jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance of the pulse generator. Test conditions for propagation delays are given in Table 10, test conditions for slew rate are given in Table 8
Fig 8. Table 10. Output An Bn, Yn
Test circuit for An, Bn and Yn outputs; slew rate B/Y side Test conditions for An, Bn and Yn outputs VI 3.0 V 3.0 V VM 1.5 V 1.5 V Repetition rate 1 MHz 1 MHz tW 500 ns 500 ns tr
3 ns 3 ns
tf
3 ns 3 ns
Switch position tPLH, tPZH GND GND tPHL, tPHZ GND VEXT = 2.8 V
VCC IO DUT VCC / 2
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IO is measured by forcing 0.5VCC on the output. The output impedance can then be calculated as Ro = 0.5VCC / |IO|.
Fig 9.
Output impedance
PDI1284P11_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
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NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
D
E
A X
c y HE vM A
Z 48 25
Q A2 A1 (A 3) Lp 1 bp 24 wM L detail X A
pin 1 index
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT370-1 (SSOP48)
PDI1284P11_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
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NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT362-1 (TSSOP48)
PDI1284P11_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
13 of 16
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PDI1284P11
3.3 V parallel interface transceiver/buffer
13. Abbreviations
Table 11. Acronym CDM CMOS DUT ECP EPP ESD HBM LSTTL MM TTL Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test Extended Capability Port Enhanced Parallel Port ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic
14. Revision history
Table 12. Revision history Release date 20080825 Data sheet status Product data sheet Change notice Supersedes PDI1284P11_2 Document ID PDI1284P11_3 Modifications:
* * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Quick reference table removed. Table 7, tPHL: Maximum value of 20 ns replaced by 23 ns. Table 11: Abbreviations list added. Product specification Product specification PDI1284P11_1 -
PDI1284P11_2 PDI1284P11_1
19990917 19970915
PDI1284P11_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
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PDI1284P11
3.3 V parallel interface transceiver/buffer
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PDI1284P11_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 25 August 2008
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PDI1284P11
3.3 V parallel interface transceiver/buffer
17. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function selection. . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 August 2008 Document identifier: PDI1284P11_3

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